The invention relates generally to semiconductor devices and more particularly to a semiconductor memory device and a process for forming such a semiconductor memory device.
Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile data storage. As is known, EEPROM device structures commonly include a floating gate that has charge storage capabilities. Charge can be forced into the floating gate structure or removed from the floating gate structure through the use of control voltages. The conductivity of the channel underlying the floating gate is significantly reduced by the presence of charges stored in the floating gate. The difference in conductivity due to a charged or uncharged floating gate can be current sensed, thus allowing binary memory states can be determined. The conductivity difference is also represented by shift in the threshold voltage (VT) associated with the device in the two different states where charge is either stored or not stored on the floating gate.
As semiconductor devices continue to evolve, the operating voltages of such semiconductor devices are often reduced in order to suit low power applications. It is desirable for such operating voltage reductions to be accomplished while ensuring speed and functionality of the devices. A controlling factor in the operating voltages required to program and erase devices with floating gates is the thickness of the tunnel oxide through which carriers are exchanged between the floating gate of the device and the underlying channel region.
In many prior art devices, the floating gate is constructed from a uniform layer of material such as doped polysilicon. In such prior art device structures, a thin tunnel oxide layer beneath the floating gate presented the potential problem of charge leakage from the floating gate to the underlying channel through defects in the thin tunnel oxide layer. Such charge leakage leads to degradation of the memory state stored within the device and is therefore undesirable. In order to avoid such charge leakage, tunnel oxide thickness was often increased. However, thicker tunnel oxide dielectric requires higher (programming and erasing) voltages for storing and removing charge from the floating gate as the charge carriers must pass through the thicker tunnel dielectric. In many cases, higher programming voltages require the implementation of charge pumps on integrated circuits in order to increase the supply voltage to meet programming voltage requirements. Such charge pumps consume a significant amount of die area for the integrated circuit and therefore reduce the memory array area efficiency and increase overall costs.
In order to reduce the required thickness of the tunnel dielectric (which may also be referred to as the tunnel oxide) and improve the area efficiency of the memory structures by eliminating the need for charge pumps, the uniform layer of material used for the floating gate may be replaced with a plurality of isolated storage elements. These isolated storage elements together provide adequate charge storage capacity while remaining physically isolated from each other such that any leakage occurring with respect to a single storage element does not cause charge to be drained from additional storage elements. As such, thinner tunnel oxides can be used in device structures and the effects of leakage occurring in such thin tunnel oxide devices does not cause the loss of state information that occurs in transistors that include a continuous-layer floating gate.
A limiting factor in construction of devices that include floating gates made up of a plurality of isolated storage elements relates to controlling the size, density, and uniformity of the isolated storage elements within the floating gate structure. The density of the isolated storage elements is important in the determination of the change in the threshold voltage for the device between the states where the floating gate is charged or discharged. Higher densities are desirable as they lead to an increased change in threshold voltage when the charge density per storage element is fixed. Prior art techniques for forming isolated storage elements on the tunnel oxide were limited to a density of approximately 5xc3x971011 isolated storage elements per cm2. With such a limited density of isolated storage elements, the charge density per storage element, or number of carriers that each storage element must retain, is forced to an elevated level to ensure a sufficient threshold voltage shift that can be robustly sensed. However, this typically leads to charge loss from individual storage elements, thus degrading the overall charge retention characteristics of the floating gate. In addition to this limitation, the limited charge storage element density of prior art devices requires longer programming times as a longer time period is required for forcing subsequent charge carriers into each storage element after an initial carrier has been stored, and the time required continues to increase as the charge density per storage element is elevated.
The techniques used for forming the isolated storage elements in such prior art devices that are limited in storage element density typically involves techniques such as low pressure chemical vapor deposition (LPCVD) and recrystallization of a thin amorphous layer of material to form the isolated storage elements. Both of these techniques require control of nucleation and growth kinetics. Since nucleation and growth kinetics typically occur concurrently, and the control of size and density of the isolated storage elements that are formed as a result of these steps is difficult.
Therefore, a need exists for a method for including isolated storage elements within semiconductor devices in a manner that provides a high density of storage elements while maintaining control over the size dispersion of the storage elements.